1. Field of the Invention
The embodiments described below are related to non-volatile memory devices, and more particularly to systems and methods for improving the reliability of non-volatile memory devices.
2. Background of the Invention
Conventional non-volatile memory devices rely on floating gate technology, or a trapping layer construction to store charge that can then be read out of the device. Such non-volatile memory devices can be viewed as enhancements to the standard metal oxide semiconductor (MOS) transistor. As is well understood, a MOS transistor comprises three main terminals: a source, a drain, and a gate. A potential applied to the gate directly controls the formation and conductivity of a channel formed below the gate between the source and drain. The conductivity of the channel affects the flow of current between the source and drain terminals. The channel becomes significantly conductive as the gate potential exceeds a certain threshold, referred to as the transistor's threshold voltage.
A floating gate memory cell differs from a standard MOS transistor in that it has an additional electrically isolated gate, a floating gate, below the standard control gate and above the transistor channel. Such a floating gate is typically composed of a conducting material, such as a polysilicon layer. A floating gate memory device stores information by holding electric charge within a floating gate. Adding or removing charge from the floating gate changes the threshold voltage of the cell, thereby defining whether the memory cell is in a programmed or erase state. Charge flowing in the channel can then be attracted to, or injected into the floating gate or trapping layer.
Charge trapping structures, such as nitride read-only memory structures, on the other hand, include a trapping nitride layer configure to store the charge instead of a floating gate suspended above the cell. FIG. 1 is a diagram illustrating a conventional nitride read-only memory structure 100. As can be seen, nitride read-only memory 100 is constructed on a silicon substrate 102. The silicon substrate can be a P-type silicon substrate or an N-type silicon substrate; however, for various design reasons P-type silicon substrates are often preferred. Drain/source regions 104 and 106 can then be implanted in substrate 102. A trapping structure 108 is then configured on substrate 102 between source/drain regions 104 and 106. Control gate 110 is then formed on top of trapping layer 108.
Drain/source regions 104 and 106 are silicon regions that are doped to be the opposite type as that as substrate 102. For example, where a P-type silicon substrate 102 is used, N-type drain/source regions 104 and 106 can be implanted therein.
Charge trapping structure 108 comprises a nitride trapping layer as well as an isolating oxide layer between the trapping layer and the channel in substrate 102. In other embodiments, trapping structure 108 can comprise a nitride trapping layer sandwiched between two isolating, or dielectric layers, such as oxide layers. Such a configuration is often referred to as an Oxide-Nitride-Oxide (ONO) trapping layer.
Charge can be accumulated and confined within trapping structure 108 next to drain/source regions 104 and 106, effectively storing two separate and independent charges. Each charge can be maintained in one of two states, either programmed or erased, represented by the presence or absence of a pocket of trapped electrons. This enables the storage of two bits of information without the complexities associated with multilevel cell technology.
Each storage area in nitride read-only memory cell 100 can be programmed independently of the other storage area. A nitride read-only memory cell is programmed by applying a voltage that causes negatively charged electrons to be injected into the nitride layer of trapping structure 108 near one end of the cell. Erasing is accomplished by applying voltages that cause holes to be injected into the nitride layer where they can compensate for electrons previously stored in the nitride layer during programming.
In general, because the stored charge is confined next to the drain/source regions within the trapping layer, numerous program —recycles can be performed without significantly degrading the cell's performance. Unfortunately, the interface trap density (Dit) increases as nitride read-only memory device 100 is cycled. The cycles induce interface traps, i.e., traps at the interface between charge trapping structure 108 and substrate 102. These interface traps will then trap charge at the interface between trapping structure 108 and substrate 102. The interface trap density (Dit) is a measure of the amount of trapped charge per cm2.
The cycling-induced interface traps will cause swings in the I-V curve for nitride read-only memory device 100 as well as threshold voltage shifts. The I-V swings and threshold voltage shifts can degrade the performance of nitride read-only memory device 100.
For example, the interface traps can cause nitride read-only memory device 100 to pass a program verify operation with much fewer electrons trapped in charge trapping structure 108 than it would typically take for a newer device to pass a program verify operation. Further, high temperature baking anneals the traps, leading to further threshold voltage loss. Thus, cycled nitride read-only memory devices cannot retain their data well in a high temperature environment.
Similar cycle induced interface traps can occur in other non-volatile memory devices, such as the floating gate devices described above. As a result, the performance of non-volatile memory devices can be improved by reducing the interface trap density.